TSMC Unveils Breakthroughs in CFET Technology at IEDM 2025: A Leap Towards Future Semiconductor Innovation
At the recently concluded International Electron Devices Meeting (IEDM) 2025, Taiwan Semiconductor Manufacturing Company (TSMC) made a landmark announcement, confirming the successful operation of integrated circuits utilizing the next-generation transistor technology known as Complementary Field-Effect Transistor (CFET). This development signifies a crucial advancement in semiconductor design, promising to enhance transistor density and performance for future electronic devices.
Key Achievements Highlighted at IEDM 2025
TSMC revealed two major milestones during the conference:
-
101-stage 3D Monolithic CFET Ring Oscillator:
This fully functional ring oscillator comprises an enabling NAND logic element and 100 inverter stages, totaling 101 stages. Comprising between 800 to 1000 transistors, the circuit serves as a fundamental building block for logic circuits. It operates efficiently within a voltage range of 0.5V to 0.95V, with oscillation frequency improving and stabilizing as voltage increases. -
World’s Smallest 6T SRAM Bit Cell:
TSMC developed two variants of this SRAM cell—the High-Density (HD) type focusing on compactness, and the High-Current (HC) type emphasizing performance. The HD variant occupies 30% less area compared to similar cells based on nanosheet FET (NS FET) technology, while HC offers read currents 1.7 times greater than HD. Both types demonstrated reliable operation within voltages ranging from 0.3V to 1.0V. This advancement directly supports denser and more efficient memory applications.
Technical Innovations Driving CFET Progress
Building on previous nanosheet-based architectures, TSMC researchers introduced novel integration techniques to reduce the gate pitch to below 48nm. Among them:
- Nanosheet Cut Isolation (NCI): This technology improves electrical isolation between adjacent FETs, minimizing leakage and enhancing performance.
- Butt Contact (BCT) Interconnection: Essential for the SRAM’s cross-coupling inverter circuits, BCT enables effective vertical connectivity between stacked transistors.
These innovations shift CFET development beyond single-transistor optimization towards full circuit-level integration, marking meaningful progress toward practical applications in logic and memory devices.
Understanding CFET Technology and Its Challenges
CFET technology stacks n-channel and p-channel FETs vertically within a single monolithic structure, effectively doubling transistor density compared to current nanosheet FET designs. However, manufacturing such vertically integrated devices is highly complex. The process requires precision in stacking and electrically isolating transistors, which increases fabrication difficulty significantly.
Until recently, most CFET research focused on individual transistors or simple inverter elements. TSMC’s demonstration of complex integrated circuits like the 101-stage ring oscillator and functional 6T SRAM cells underscores the transition to more advanced, scalable CFET applications.
Roadmap and Future Prospects
TSMC aims to bring CFET technology into practical use in the 2030s. Although current prototypes are in early developmental stages, the potential to continue Moore’s Law by enhancing transistor density while maintaining performance and energy efficiency is promising.
Additionally, TSMC is advancing new interconnection technologies to improve overall chip performance, including:
- A novel via scheme for copper interconnections to reduce resistance and capacitance.
- Innovative copper barrier layers to decrease wire resistance.
- Exploration of new metal materials featuring air gaps and intercalated graphene to minimize interconnection delays.
Industry-Wide Momentum Toward CFET
TSMC is not alone in pursuing CFET innovations. Semiconductor giants like Samsung and Intel are actively developing similar technologies:
- Intel: Demonstrated early CFET inverters back in 2020 with a unique backside power delivery system to simplify interconnections below the silicon wafer, achieving compact designs with a contacted poly pitch of 60nm.
- Samsung: Showcased 3D stacked FET (3DSFET) devices with 48nm and 45nm pitches and focused on dry etching processes to improve electrical isolation and device yield. Samsung’s implementation includes contacting the devices from below, similar to Intel, but with a different nanosheet stacking approach.
Collaborative efforts such as IBM Research and Samsung’s “Monolithic Stacked Field-Effect Transistor” prototype further highlight the industry’s concerted push to overcome CFET manufacturing challenges and realize its potential.
Conclusion: CFET—The Next Frontier in Semiconductor Technology
CFET technology represents a vital pathway for advancing transistor integration beyond the limitations of current FinFET and nanosheet FET structures. While significant engineering hurdles remain, TSMC’s breakthroughs at IEDM 2025 signal accelerating progress toward the scalable application of CFET-based logic and memory circuits.
As the semiconductor industry gears up for this transformative shift, CFET holds the promise of sustaining Moore’s Law and powering the next generation of high-performance, energy-efficient electronic devices well into the coming decades.
